XC2S200-5FGG456C

Product Summary

The XC2S200-5FGG456C is a member of Spartan-II Field-Programmable Gate Array family gives users high performance, abundant logic resources, and a rich feature set, all at an exceptionally low price. The XC2S200-5FGG456C offers densities ranging from 15,000 to 200,000 system gates. System performance is supported up to 200 MHz. Features include block RAM (to 56K bits), distributed RAM (to 75,264 bits), 16 selectable I/O standards, and four DLLs. Fast, predictable interconnect means that successive design iterations continue to meet timing requirements. The XC2S200-5FGG456C is a superior alternative to mask-programmed ASICs. The FPGA XC2S200-5FGG456C avoids the initial cost, lengthy development cycles, and inherent risk of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary (impossible with ASICs).

Parametrics

XC2S200-5FGG456C absolute maximum ratings: (1)VCCINT, Supply voltage relative to GND: –0.5 to 3.0 V; (2)VCCO, Supply voltage relative to GND: –0.5 to 4.0 V; (3)VREF, Input reference voltage: –0.5 to 3.6 V; (4)VIN, Input voltage relative to GND:5V tolerant I/O: –0.5 to 5.5 V; No 5V tolerance: –0.5 to VCCO+0.5 V; (5)VTS, Voltage applied to 3-state output: 5V tolerant I/O: –0.5 to 5.5 V; No 5V tolerance: –0.5 to VCCO+0.5 V; (6)TSTG, Storage temperature (ambient): –65 to +150 ℃ ; (7)TJ, Junction temperature: +135 ℃ max.

Features

XC2S200-5FGG456C features: (1)Second generation ASIC replacement technology; (2)Versatile I/O and packaging: Pb-free package options; Low-cost packages available in all densities; Family footprint compatibility in common packages; 16 high-performance interface standards; Hot swap Compact PCI friendly; Zero hold time simplifies system timing; (3)Fully supported by powerful Xilinx development system: Foundation ISE Series: Fully integrated software; alliance Series: For use with third-party tools; Fully automatic mapping, placement, and routing.

Diagrams