CY7C1354C-200AXCT

Product Summary

The CY7C1354C-200AXCT is a 3.3V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAM with No Bus Latency (NoBL) logic, respectively. The CY7C1354C-200AXCT is designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354C-200AXCT is equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. The CY7C1354C-200AXCT is pin compatible and functionally equivalent to ZBT devices.

Parametrics

CY7C1354C-200AXCT absolute maximum ratings: (1)Storage Temperature: –65 to +150℃; (2)Ambient Temperature with Power Applied: –55 to +125℃; (3)Supply Voltage on VDD Relative to GND: –0.5V to +4.6V; (4)Supply Voltage on VDDQ Relative to GND: –0.5V to +VDD; (5)DC to Outputs in Tri-State: –0.5V to VDDQ + 0.5V; (6)DC Input Voltage: –0.5V to VDD + 0.5V; (7)Current into Outputs (LOW): 20 mA; (8)Static Discharge Voltage: > 2001V; (9)Latch-up Current: > 200 mA.

Features

CY7C1354C-200AXCT features: (1)Pin-compatible and functionally equivalent to ZBT; (2)Supports 250-MHz bus operations with zero wait states: Available speed grades are 250, 200, and 166 MHz; (3)Internally self-timed output buffer control to eliminate the need to use asynchronous OE; (4)Fully registered (inputs and outputs) for pipelined operation; (5)Byte Write capability; (6)Single 3.3V power supply (VDD); (7)3.3V or 2.5V I/O power supply (VDDQ); (8)Fast clock-to-output times: 2.8 ns (for 250-MHz device); (9)Clock Enable (CEN) pin to suspend operation; (10)Synchronous self-timed writes; (11)Available in lead-free 100-Pin TQFP package, lead-free and non lead-free 119-Ball BGA package and 165-Ball FBGA package; (12)IEEE 1149.1 JTAG-Compatible Boundary Scan; (13)Burst capability–linear or interleaved burst order; (14)ZZ Sleep Mode option and Stop Clock option.

Diagrams