DSPIC30F3013-20E/SO

Product Summary

The DSPIC30F3013-20E/SO is a high-performance digital signal controller. The DSPIC30F3013-20E/SO can be placed in the Gated Time Accumulation mode. This mode allows the internal TCY to increment the respective timer when the gate input signal (T1CK pin) is asserted high. Control bit TGATE (T1CON<6>) must be set to enable this mode. The timer must be enabled (TON = 1) and the timer clock source set to internal (TCS = 0). The input clock (FOSC/4 or external clock) to the 16-bit. The DSPIC30F3013-20E/SO has a prescale option of 1:1, 1:8, 1:64 and 1:256, selected by control bits TCKPS<1:0> (T1CON<5:4>). The DSPIC30F3013-20E/SO has the ability to generate an interrupt on period match. When the DSPIC30F3013-20E/SO count matches the Period register, the T1IF bit is asserted and an interrupt will be generated if enabled.

Parametrics

DSPIC30F3013-20E/SO absolute maximum ratings: (1)Ambient temperature under: -40℃ to +125℃; (2)Storage temperature: -65℃ to +150℃; (3)Voltage on any pin with respect to VSS (except VDD and MCLR): -0.3V to (VDD + 0.3V); (4)Voltage on VDD with respect to VSS: -0.3V to +5.5V; (5)Voltage on MCLR with respect to: 0V to +13.25V; (6)Maximum current out of VSS pin: 300 mA; (7)Maximum current into VDD pin: 250 mA; (8)Input clamp current, IIK (VI < 0 or VI > VDD): ±20 mA; (9)Output clamp current, IOK (VO < 0 or VO > VDD): ±20 mA; (10)Maximum output current sunk by any I/O: 25 mA; (11)Maximum output current sourced by any I/O pin: 25 mA; (12)Maximum current sunk by all ports: 200 mA; (13)Maximum current sourced by all ports: 200 mA.

Features

DSPIC30F3013-20E/SO features: (1)Modified Harvard architecture; (2)C compiler optimized instruction set architecture; (3)Flexible addressing modes; (4)84 base instructions; (5)24-bit wide instructions, 16-bit wide data path; (6)Up to 24 Kbytes on-chip Flash program space; (7)Up to 2 Kbytes of on-chip data RAM; (8)Up to 1 Kbytes of non-volatile data EEPROM; (9)16 x 16-bit working register array; (10)Up to 30 MIPs operation: DC to 40 MHz external clock input; 4 MHz-10 MHz oscillator input with PLL active (4x, 8x, 16x); (11)Up to 21 interrupt sources: 8 user selectable priority levels; 3 external interrupt sources; 4 processor trap sources.

Diagrams