Product Summary

The EP20K60EFC324-2 is a Programmable Logic Device. It is designed with the MultiCore architecture, which combines the strengths of LUT-based and productterm-based devices with an enhanced memory structure. LUT-based logic of the EP20K60EFC324-2 provides optimized performance and efficiency for data-path, registerintensive, mathematical, or digital signal processing (DSP) designs. The EP20K60EFC324-2 includes additional features such as advanced I/O standard support, CAM, additional global clocks, and enhanced ClockLock clock circuitry.

Parametrics

EP20K60EFC324-2 absolute maximum ratings: (1)VCCINT Supply voltage: –0.5 to 3.6 V; (2)VCCIO: –0.5 to 4.6 V; (3)VI DC input voltage: –2.0 to 5.75 V; (4)IOUT DC output current, per pin: –25 to 25 mA; (5)TSTG Storage temperature: –65 to 150 ℃; (6)TAMB Ambient temperature: –65 to 135 ℃; (7)TJ Junction temperature: 135 ℃.

Features

EP20K60EFC324-2 features: (1)Industry’s first programmable logic device (PLD) incorporating system-on-a-programmable-chip (SOPC) integration: MultiCore architecture integrating look-up table (LUT) logic, product-term logic, and embedded memory, LUT logic used for register-intensive functions, Embedded system block (ESB) used to implement memory functions, including first-in first-out (FIFO) buffers, dual-port RAM, and content-addressable memory (CAM), ESB implementation of product-term logic used for combinatorial-intensive functions; (2)High density: 30,000 to 1.5 million typical gates, Up to 51,840 logic elements (LEs), Up to 442,368 RAM bits that can be used without reducing available logic, Up to 3,456 product-term-based macrocells.

Diagrams

EP20K60EFC324-2 circuit diagram

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Data Sheet

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Data Sheet

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5-10: $20.65
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Data Sheet

0-1: $42.59
1-2: $39.19
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