Product Summary

The GAL18V10B-15LP, at 7.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide a very flexible 20-pin PLD. CMOS circuitry allows the GAL18V10B-15LP to consume much less power when compared to its bipolar counterparts. The E2 technology offers high speed (<100ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently.

Parametrics

GAL18V10B-15LP absolute maximum ratings: (1)Supply voltage VCC: -0.5 to +7V; (2)Input voltage applied: -2.5 to VCC +1.0V; (3)Off-state output voltage applied: -2.5 to VCC +1.0V; (4)Storage Temperature: -65 to 150℃; (5)Ambient Temperature with Power Applied: -55 to 125℃.

Features

GAL18V10B-15LP features: (1)HIGH PERFORMANCE E2CMOS TECHNOLOGY; (2)LOW POWER CMOS; (3)ACTIVE PULL-UPS ON ALL PINS; (4)E2CELL TECHNOLOGY; (5)TEN OUTPUT LOGIC MACROCELLS; (6)PRELOAD AND POWER-ON RESET OF REGISTERS: 100% Functional Testability.

Diagrams

GAL18V10B-15LP functional block diagram

Image Part No Mfg Description Data Sheet Download Pricing
(USD)
Quantity
GAL18V10B-15LP
GAL18V10B-15LP

Lattice

SPLD - Simple Programmable Logic Devices 18 Input 10 Output 5V Low Power 15ns

Data Sheet

0-360: $1.71
Image Part No Mfg Description Data Sheet Download Pricing
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GAL16LV8
GAL16LV8

Other


Data Sheet

Negotiable 
GAL16LV8C-10LJ
GAL16LV8C-10LJ

Lattice

SPLD - Simple Programmable Logic Devices LO VOLT E2CMOS PLD

Data Sheet

Negotiable 
GAL16LV8C-10LJN
GAL16LV8C-10LJN

Lattice

SPLD - Simple Programmable Logic Devices LO VOLT E2CMOS PLD

Data Sheet

Negotiable 
GAL16LV8C-15LJ
GAL16LV8C-15LJ

Lattice

SPLD - Simple Programmable Logic Devices LO VOLT E2CMOS PLD

Data Sheet

Negotiable 
GAL16LV8C-15LJN
GAL16LV8C-15LJN

Lattice

SPLD - Simple Programmable Logic Devices LO VOLT E2CMOS PLD

Data Sheet

Negotiable 
GAL16LV8C-7LJ
GAL16LV8C-7LJ

Lattice

SPLD - Simple Programmable Logic Devices LO VOLT E2CMOS PLD

Data Sheet

Negotiable