Product Summary

The TL16PNP550AFN is an asynchronous communications element with PLUG-and-PLAY (PnP) and autoflow control. Functionally equivalent to the TL16C450 on power up (character or TL16C450 mode), the TL16PNP550AFN, like the TL16C550C, can be placed in an alternate mode (FIFO mode). The TL16PNP550AFN relieves the CPU of excessive software overhead by buffering received and transmitted characters. The receiver and transmitter FIFOs store up to 16 bytes including three additional bits of error status per byte for the receiver FIFO. In the FIFO mode, there is a selectable autoflow control feature that can significantly reduce software overload and increase system efficiency by automatically controlling serial data flow using RTS output and CTS input signals.

Parametrics

TL16PNP550AFN absolute maximum ratings: (1)Supply voltage range, VCC: –0.5V to 7V; (2)Input voltage range at any input, VI: –0.5V to 7V; (3)Output voltage range, VO:–0.5V to 7V; (4)Operating free-air temperature range, TA: 0℃ to 70℃; (5)Storage temperature range, Tstg: -65℃ to 150℃; (6)Case temperature for 10 seconds, TC: FN package: 260℃.

Features

TL16PNP550AFN features: (1)PnP Card Autoconfiguration Sequence Compliant; (2)External Terminal-to-Bypass PnP Autoconfiguration Sequence; (3)In UART Bypass Mode, the Stand-Alone PnP Controller is Configured With One Logical Device; (4)Provides 10-Interrupts IRQ3–IRQ7, IRQ9–IRQ12, IRQ15; (5)Simple 3-Pin Interface to SGS-ThomsonE EEPROM 2K/4K ST93C56/66; (6)High Output Current Drive. No External Buffer Needed for Data and Interrupt Signals; (7)Programmable Auto-RTS and Auto-CTS; (8)In Auto-CTS Mode, CTS Controls Transmitter; (9)In Auto-RTS Mode, Receiver FIFO Contents and Threshold Control RTS; (10)The Serial and Modem Control Outputs Drive a 1-Meter RJ11 Cable Directly if Equipment Is on the Same Power Drop; (11)Capable of Running With All Existing TL16C450 Software; (12)After Reset, All Registers Are Identical to the TL16C450 Register Set; (13)Clock Prescalar Allows 22-MHz Oscillator Clock to be Divided by 12, 6, 3, or 1; (14)In the TL16C450 Mode, Hold and Shift Registers Eliminate the Need for Precise Synchronization Between the CPU and Serial Data; (15)Programmable Baud Rate Generator Allows Division of Any Input Reference Clock by 1 to (216 –1) and Generates an Internal 16×Clock; (16)On-Chip I/O Port Address Decoding; (17)In PnP Bypass Mode, 6 External Terminals Configure the I/O Base Address and Interrupt Mapping; (18)Adds or Deletes Standard Asynchronous Communication Bits (Start, Stop, and Parity) to or From the Serial Data Stream; (19)Independent Control of Transmit, Receive, Line Status, and Data Set Interrupts on Each Channel; (20)False Start Bit Detection; (21)Complete Status Reporting Capabilities; (22)3-State Outputs Provide TTL Drive for Bidirectional Data Bus and Interrupt Lines; (23)Line Break Generation and Detection; (24)Fully Prioritized Interrupt System Controls; (25)Modem Control Functions (CTS, RTS, DSR, DTR, RI, and DCD); (26)Transmitter and Receiver Run at the Same Speed; (27)Up to 16-MHz Clock Rate for Up to 1-Mbaud Operation for the Internal ACE; (28)Available in 68-Pin PLCC.

Diagrams

TL16PNP550AFN block diagram

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