Product Summary

The TMS320VC5410AGGV12 is a fixed-point, digital signal processor (DSP) (hereafter referred to as the 5410A unless otherwise specified). The TMS320VC5410AGGV12 is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor TMS320VC5410AGGV12 provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.

Parametrics

TMS320VC5410AGGV12 absolute maximum ratings: (1)DVDD, Supply voltage I/O range: –0.3V to 4.0V; (2)CVDD, Supply voltage core range: –0.3V to 2.0V; (3)VI, Input voltage range: –0.3V to 4.5V; (4)VO, Output voltage range: –0.3V to 4.5V; (5)TC, Operating case temperature range: –40 to 100℃; (6)Tstg, Storage temperature range: –55 to 150℃.

Features

TMS320VC5410AGGV12 features: (1)Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus; (2)40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators; (3)17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation; (4)Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator; (5)Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle; (6)Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs); (7)Data Bus With a Bus Holder Feature; (8)Extended Addressing Mode for 8M × 16-Bit Maximum Addressable External Program.

Diagrams

TMS320VC5410AGGV12 circuit diagram

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