(China (Mainland))
Product Summary
The XC5VLX30-1FFG676I is a phase locked loop. It contains up to six CMT tiles. The PLL main purpose is to serve as a frequency synthesizer for a wide range of frequencies, and to serve as a jitter filter for either external or internal clocks in conjunction with the DCMs of the CMT.
Parametrics
XC5VLX30-1FFG676I absolute maixmum ratings: (1)VCCINT Internal supply voltage relative to GND: –0.5 to 1.1 V; (2)VCCAUX Auxiliary supply voltage relative to GND: –0.5 to 3.0 V; (3)VCCO Output drivers supply voltage relative to GND: –0.5 to 3.75 V; (4)VBATT Key memory battery backup supply: –0.5 to 4.05 V; (5)VREF Input reference voltage: –0.5 to 3.75 V; (6)IIN Current applied to an I/O pin, powered or unpowered: ±100 mA; (7)TSTG Storage temperature (ambient): –65 to 150 ℃; (8)TSOL Maximum soldering temperature: +220 ℃; (9)TJ Maximum junction temperature: +125 ℃.
Features
XC5VLX30-1FFG676I features: (1)18, 36, or 72-bit wide ports can have an individual write enable per byte. This feature is popular for interfacing to an on-chip microprocessor; (2)Each block RAM contains optional address sequencing and control circuitry to operate as a built-in multirate FIFO memory. In Virtex-5 architecture, the block RAM can be configured as an 18Kb or 36Kb FIFO; (3)All inputs are registered with the port clock and have a setup- to-clock timing specification; (4)A write operation requires one clock edge.
Diagrams
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 XC5VLX30-1FFG676I |
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IC FPGA VIRTEX-5 30K 676FBGA |
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